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INTEGER |
t1e1TimingOther(1), t1e1TimingInternal(2), t1e1TimingNetwork(3), t1e1TimingT1DTE(4), t1e1TimingStation(5), t1e1TimingStaClock(6), t1e1TimingPort1(7), t1e1TimingPort2(8), t1e1TimingPort3(9), t1e1TimingPort4(10), t1e1TimingPort5(11), t1e1TimingPort6(12), t1e1TimingPort7(13), t1e1TimingPort8(14), t1e1TimingPort9(15), t1e1TimingPort10(16), t1e1TimingPort11(17), t1e1TimingPort12(18), t1e1TimingPort13(19), t1e1TimingPort14(20), t1e1TimingPort15(21), t1e1TimingPort16(22), t1e1TimingPort17(23), t1e1TimingPort18(24), t1e1TimingPort19(25), t1e1TimingPort20(26), t1e1TimingPort21(27), t1e1TimingPort22(28), t1e1TimingPort23(29), t1e1TimingPort24(30), t1e1TimingPort25(31), t1e1TimingPort26(32), t1e1TimingPort27(33), t1e1TimingPort28(34), t1e1TimingPort29(35), t1e1TimingPort30(36), t1e1TimingPort31(37), t1e1TimingPort32(38), t1e1TimingSlot2PortA(39), t1e1TimingSlot2PortB(40), t1e1TimingSlot3PortA(41), t1e1TimingSlot3PortB(42), t1e1TimingSlot4PortA(43), t1e1TimingSlot4PortB(44), t1e1TimingSlot5PortA(45), t1e1TimingSlot5PortB(46), t1e1TimingSlot6PortA(47), t1e1TimingSlot6PortB(48), t1e1TimingSlot2Dsu1PortA(49), t1e1TimingSlot2Dsu1PortB(50), t1e1TimingSlot2Dsu2PortA(51), t1e1TimingSlot2Dsu2PortB(52), t1e1TimingSlot2Dsu3PortA(53), t1e1TimingSlot2Dsu3PortB(54), t1e1TimingSlot2Dsu4PortA(55), t1e1TimingSlot2Dsu4PortB(56), t1e1TimingSlot2Dsu5PortA(57), t1e1TimingSlot2Dsu5PortB(58), t1e1TimingSlot2Dsu6PortA(59), t1e1TimingSlot2Dsu6PortB(60), t1e1TimingSlot3Dsu1PortA(61), t1e1TimingSlot3Dsu1PortB(62), t1e1TimingSlot3Dsu2PortA(63), t1e1TimingSlot3Dsu2PortB(64), t1e1TimingSlot3Dsu3PortA(65), t1e1TimingSlot3Dsu3PortB(66), t1e1TimingSlot3Dsu4PortA(67), t1e1TimingSlot3Dsu4PortB(68), t1e1TimingSlot3Dsu5PortA(69), t1e1TimingSlot3Dsu5PortB(70), t1e1TimingSlot3Dsu6PortA(71), t1e1TimingSlot3Dsu6PortB(72), t1e1TimingSlot4Dsu1PortA(73), t1e1TimingSlot4Dsu1PortB(74), t1e1TimingSlot4Dsu2PortA(75), t1e1TimingSlot4Dsu2PortB(76), t1e1TimingSlot4Dsu3PortA(77), t1e1TimingSlot4Dsu3PortB(78), t1e1TimingSlot4Dsu4PortA(79), t1e1TimingSlot4Dsu4PortB(80), t1e1TimingSlot4Dsu5PortA(81), t1e1TimingSlot4Dsu5PortB(82), t1e1TimingSlot4Dsu6PortA(83), t1e1TimingSlot4Dsu6PortB(84), t1e1TimingSlot5Dsu1PortA(85), t1e1TimingSlot5Dsu1PortB(86), t1e1TimingSlot5Dsu2PortA(87), t1e1TimingSlot5Dsu2PortB(88), t1e1TimingSlot5Dsu3PortA(89), t1e1TimingSlot5Dsu3PortB(90), t1e1TimingSlot5Dsu4PortA(91), t1e1TimingSlot5Dsu4PortB(92), t1e1TimingSlot5Dsu5PortA(93), t1e1TimingSlot5Dsu5PortB(94), t1e1TimingSlot5Dsu6PortA(95), t1e1TimingSlot5Dsu6PortB(96), t1e1TimingSlot6Dsu1PortA(97), t1e1TimingSlot6Dsu1PortB(98), t1e1TimingSlot6Dsu2PortA(99), t1e1TimingSlot6Dsu2PortB(100), t1e1TimingSlot6Dsu3PortA(101), t1e1TimingSlot6Dsu3PortB(102), t1e1TimingSlot6Dsu4PortA(103), t1e1TimingSlot6Dsu4PortB(104), t1e1TimingSlot6Dsu5PortA(105), t1e1TimingSlot6Dsu5PortB(106), t1e1TimingSlot6Dsu6PortA(107), t1e1TimingSlot6Dsu6PortB(108) |
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